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No, Inputs should not be left floating. Pull DOWN pin 23 (S_CFN_L) secondary bus arbiter select. Pull DOWN pin 126 MSK_IN to turn on all the secondary bus clocks without programming through GPIO. REQ signals should have pull-Ups to Vio. See Application Notes 55 , 58 , 60 for further details.
Yes, you can have the secondary bus running at similar speed at the primary, or you can have the secondary bus running at half the speed of the primary bus. So, if the primary bus is running at 66 MHz then the secondary bus can be running at 33 MHz or 66 MHz. This is controlled by Config66 and s_m66en signals. If both are high, then the secondary will run at the same speed as the primary bus. If either one of them is low, then the secondary bus will run at half the speed of the primary bus.
Yes you can, the PCI-X specification is backward compatible with this bridge, and it will work at 66 MHz speed.
A 66 MHz bus normally drops to 33 MHz when the M66EN signal is driven low. So, you could bring down the primary bus to 33 MHz by tying or pulling low the P_M66EN signal, if that is your wish. More importantly, some other card might do this to you if it is designed for 33 MHz but plugged into a normally 66 MHz bus.
Yes. Address space is reserved in multiples of 1 Mb for the prefetchable and non-prefetchable memory spaces.
No
| No |
No, the secondary bus runs at equal or half the frequency of the primary bus.
Yes, the clock ICs’ outputs can be just left open if they are not used. In this way can save the un-used buffer output drawing power without driving anything.
Yes, you can plug it in a 64-bit slot. The system will automatically resize the slot to 32-bit, all transfers will occur at 32-bit data width.
Tie one clock to S_CLKIN (pin 51). The other unused clocks can be unconnected.By default all the clocks are enabled; unused clocks can also be turned off at the Secondary Clock Control Register (configuration register offset 68h, bits 8:0).
| Tie one clock to S_CLKIN (pin 51). The other unused clocks can be unconnected.By default all the clocks are enabled; unused clocks can also be turned off at the Secondary Clock Control Register (configuration register offset 68h, bits 8:0). |
Tie one clock to S_CLKIN (pin 21 for the FQFP 208 pin package). The other unused clocks can be unconnected; connect MSK_IN (pin 126) low to skip using the GPIO clock programming circuit and the unused clock outputs can be left no connect.
Either could work, so long as the total decoupling capacitance is provided. Our general guideline is to decouple power entering the board with .1 and 10uF caps and again for safety at the four corners of the bridge IC with .1, .01, and 10uF caps.
Yes, a Hot swap controller is needed to ramp up the power as needed. It will also shut down if there is something wrong and there is too much current flowing through the Vcc planes.
Our bridge doesn't need a Pericom specific device driver. At the Windows 2000/XP level, the generic pci-pci bridge driver pci.sys is all that is needed, which comes with every windows. Linux (Red Hat 7) supported our bridge with no driver from us, using a default pci-pci bridge driver.
| Our bridge doesn't need a Pericom specific device driver. At the Windows 2000/XP level, the generic pci-pci bridge driver pci.sys is all that is needed, which comes with every windows. Linux (Red Hat 7) supported our bridge with no driver from us, using a default pci-pci bridge driver. |
P_Vio and S_Vio pins at our bridges control "output driving strength", which is related to current not voltage levels. The V/I curves between 3.3 V signaling and 5V signaling spec differ, and our exact pullup and pulldown curves can be viewed from our IBIS model, where "high drive" is with (P/S)_Vio input of 5V and "low drive" is (P/S)_Vio input of 3.3V.
Generally the system BIOS (in non plug and play environment) will configure the bridge -- that is, assign PCI bus number, enumerate (detect and assign address ranges) devices on the secondary buses, and update the memory ranges assigned to each bus. The OS does this for plug and play systems. Once this much configuring is done, the bridge can forward transactions in either direction without further Pericom-specific drivers being needed. For the Windows and Linux environments the bridge uses the generic bridge driver already part of the OS kernel.
Maybe. You'll want to determine temperature at the die junction, but that involves first knowing the power, the thermal resistance (theta Ja) of the part, and the ambient air temperature. Power = Vcc * Icc. Peak traffic generates the following current at the bridge: Peak ICC @ 3.6V Vcc. 5 MHz 61 mA (all 3 buses at 5 Mhz). 33 MHz 310mA (all 3 buses at 33 MHz). 66 MHz 780 mA (all 3 buses at 66 MHz). Theta Ja for the NA272 package is 27.55 C/W. Tj = Temp_Air + Power[Theta Ja]. See Packaging Mechanicals for more information.
Yes, all these guidelines are available in the Hardware implementation Guides. All relevant Application Note/Briefs are available under the APPLICATION NOTES tab on the PRODUCT DETAIL PAGE for each product in the FINDER tool. Please refer to Bridges
Hardware Implementation Guide for PI7C8150 PCI-PCI Bridge
Hardware Implementation Guide for PI7C8152
Hardware Implementation Guide for PI7C8154.
Yes, all these guidelines are available in the Hardware implementation Guide for the PI7C8154. See Application Note 60
The 7300D and 815x family of bridges are transparent bridges.
When first powering the chip, either power the core voltage (3.3V) before powering Vio or allow 3.3V and 5V to rise together (as is normal for motherboard power supplies).
When first powering the chip, either power the core voltage (3.3V) before powering Vio or allow 3.3V and 5V to rise together (as is normal for motherboard power supplies).
The bridge does not do any cache snooping. The PCI bus is not responsible for snooping. If you think that snooping is required then you have to have your own cache controller on the PCI bus to do snooping. The bridge stores memory writes briefly but they continuously are written to the far side of the bridge. If you wish to flush the posted write buffers, your application should place an IO write or IO read command into the transaction queue. Memory writes initiated after that commands are executed after the IO transaction concludes.
No, This is a commercial level grade part only.
Each of the three buses {Primary, secondary S1, secondary S2} are independent and thus each will be arbitrated separately, regardless of activity or idle state on another bus.
Yes, depending on the state of signal S_M66EN, when the primary Clock is 66 MHz you can have both, either, or neither secondary bus set to the same speed (S_M66EN = high) or half speed of the primary bus (S_M66EN = low).
The M66EN signals are used directly to the control logic. We do not use the M66EN for strapping, (and thus the M66EN signals are "live" at all times).
The PI7C8152B was intended to be a pin compatible drop-in replacement to the Intel 21152. The drivers that currently work for the Intel device will function with our device as well. The PI7C8152B does not require any external drivers, but instead utilizes the embedded drivers in Windows. The only issue that may come up is that if your software is looking specifically for the Intel device and vendor ID's, it will need to be modified. The PI7C8152B has an added feature, it can work at 66 MHz. our device ID and vendor ID are different from Intel's.
The PI7C8150B was intended to be a pin compatible drop-in replacement to the Intel 21150. The drivers that currently work for the Intel device will function with our device as well. The PI7C8150B does not require any external drivers, but instead utilizes the embedded drivers in Windows. The only issue that may come up is that if your software is looking specifically for the Intel device and vendor ID's, it will need to be modified. Our device and vendor ID's are different from Intel's.
RESVD (pin 127 in package MA-208) is at J14, leave this as NC (no connect),RESVD (pin 128 in package MA-208) is at J16, leave this as NC (no connect).
Non-prefetchable read transactions use single DWORD data phases. Section 3.6.3 “Read Prefetch Address Boundaries” shows that Memory Read Line and Memory Read Multiple commands implicitly prefetch. Memory Read commands behave differently: For Downstream memory read commands (i.e. target device is on the secondary PCI bus), program config address 20h with your memory mapped I/O range (i.e. non-prefetch) and for config address 24h the prefetch base address needs to be *higher* than the prefetch limit address. Example: [Config register offset 24] write 0000FFFF (which will read back as 0000FFF0 as the last byte is RO) [Config register offset 28] defaults to 00000000 so the upper 32-bits for prefetch base and prefetch limit line up . Upstream defaults to PREFETCHABLE due to config offset 40h bit 4 = 0 after reset. Write offset 40h bit 4 to be "1" to turn off upstream prefetching.
At boot up, the BIOS probes each PCI bus to look for PCI devices that have memory or IO requirements. When finished reading all possible device numbers, the PCI Bridge, which owns that PCI bus, has memory ranges programmed for (I/O, non-prefetchable memory, and prefetchable memory). This continues until BIOS has found all PCI buses and all devices on those buses. After that, whenever a PCI transaction happens, the bridge checks the address of the target against the memory RANGE programmed at each bus within the BRIDGE configuration register. If the initiator is on a secondary bus and the target address is outside the ranges (start address until end address) of all the memory and I/O address registers, the transaction is forwarded to the primary PCI bus for some other device to claim it. If the initiator is on the primary PCI bus and the target address does not decode to one of the address ranges in config register 0 (for bus S1) or config register 1 (for bus S2), then the bridge does not claim the transaction. In both cases, the CPU is not used.
We recommend using Vio for pull-ups.
There are two reset bits:1- secondary reset -- bit 22 offset 3c Hex This bit will reset the secondary interface signals and the FIFOs.2- Chip reset -- bit 8 offset 40 Hex .This bit will reset the entire chip, primary, secondary bus and the FIFOs as well as the internal registers.
Yes, the primary PCI bus is idle/available for use while traffic moves from S1 to S2.
Traffic originating on a bus that has a target address decoding to the same bus is not propagated to other buses. If the target address decodes to the other secondary bus, the transaction is placed into either the posted write buffer or the delayed transaction buffer of that target bus (depending on the PCI command used) and will commence at the other bus when the bridge next receives grant from the arbiter. If the target address decodes to neither secondary bus, and is initiated from a secondary bus, the bridge forwards it to the primary PCI bus by placing the transaction into the proper FIFO for that PCI command. If the initiator is already upstream from the bridge and the target is also upstream from the bridge, the bridge does not claim the transaction. There are no "protected" or "non-transparent" address spaces; one of the above four conditions applies.
Each bridge based add-in card loads the primary PCI bus by one Load, regardless of the number of devices placed on the secondary buses of that bridge IC. PCI specification revision 2.2 allows 2 loads at 66 MHz and 4 loads at 33 MHz.
The internal arbiter has two possible priority levels for each secondary bus master device and the bridge itself. These are programmable at configuration register offset 40h. By selecting some devices as high priority and some as low priority, you can give preference to a high bandwidth or time-critical device.
This bridge is designed to Intel 21154BE capabilities (power management support at pin D11, 2KV ESD rating, 0.35 micron process, and more robust tolerances for 3.3V/5V power start up sequence.) The bridge also can be used in designs intended for 21154 versions AC, AE, and BC also.
It is recommended to use 4.7k for pull-up and 1k for pull-down even though Clock IC has internal pull-up/down as high reliability design guide, include un-used inputs pins.
PCI-to-PCI-Bridge is a chip that has a PCI interface on the one side (we call it the primary bus), and it also has another PCI Interface (this is called the secondary bus) on the other side. It is a chip that allows you to add another PCI bus onto your system.
FCP is Frequency Control Product. They include crystals, crystal oscillators (XO), voltage control oscillators (VCXO), and TCXO. XO has IC and crystal integrated together as a component for quality easy use in system designs. For more product information, please visit company website: https://www.diodes.com/products/connectivity-and-timing/crystal-and-crystal-oscillator/
LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet to prevent double termination.
This is a 32-bit, 66 MHz PCI-to-PCI bridge that adheres to the PCI specification rev 2.2, PCI-to-PCI bridge spec 1.1.
This is a 32-bit, 66 MHz PCI-to-PCI bridge that adheres to the PCI specification rev 2.2, PCI-to-PCI bridge spec 1.1.
Junction temperature, at peak traffic/peak operating frequency:Tj = Ta +P [Theta Ja]. For the ND (256 pin BGA) part, Theta Ja is 31.2 °C/watt; the MA part uses Theta Ja of 39 °C/watt. Peak traffic/66 MHz on both PCI buses uses 1.39 W power. If we use those numbers in the formula: Tj = 85 °C +1.4w[31.2 °C] ? 125.6 C (256 pin BGA, package ND)Tj = 70 °C + 1.4w[39 °C] ? 124.6 C (208 pin FQFP, package MA) We know the component performs according to all rated specifications until junction temp exceeds at least 125 C.Typical power consumption at 33 MHz primary bus /33 MHz secondary bus is somewhat less than half, around 600mW. See packaging mechanicals for more information.
The reference clock DC specifications and AC timing requirements are shown in the table below. More details can be found in "PCI Express Card Electromechanical Specification Revision 1.1", Chap 2.1.3.
Pull up the unused REQ# signals; you may use a single resistor in the 5K-8K ohm range tied to Vio to reduce parts count. GNT# is an output from our bridge IC and can be left not connected.
MS1 (pin 106 for package MA-208) is pin R16 for the BGA 8150. It is normally connected to VSS. MS0 (pin 155 for package MA-208) is pin B14 for the BGA 8150. It is normally connected to VDD.
These are actually multiplexed pins. By default, we are compatible with the Intel 21150 solution, where pin 155 is VDD, and pin 106 is VSS. In future versions of this chip, changing the setting (pulled HIGH or LOW) on these pins will allow for future features. For now, these optional capabilities are reserved.
There are many uses for this chip including:
1) To alleviate the excessive loading on the motherboard. This chip can be used on a server board, or a main board in a system that needs many I/O cards connected to it; these I/O cards can be Ethernet, Fiberchannel, SCSI, or any other PCI I/O cards. PCI specification rev 2.2 allows you to have as many as 4 slots @ 33 MHz slots and two 66 MHz slots. If your system requires more then 4 slots, then you need to add a PCI-to-PCI Bridge. This bridge will take one load only, but it will allow you to add four additional slots on the other side. See Figure 1 of Application Note 55 available on the web.
2) If you have more than one PCI interface chip on an add-in card. If you are designing an intelligent add-in card that requires a CPU and an I/O chip like Ethernet, SCSI, or Fiberchannel, then you will have two or more PCI loads, in this case you must have a PCI-to-PCI bridge on the card. The PCI specification rev 2.2 allows only one PCI Load connected to the PCI Edge connector. See Figure 3 of Application Note 55 available on the web.
3) If you have many types of interfaces, and you would like to isolate each application’s traffic to a specific bus (example: you have couple of Ethernet chips on your system that need to be 32-bit and 66 MHz and have two low-performance 32-bit applications like modem cards running at 33 MHz). In this case, to isolate the two distinct applications you would add one bridge for the 66 MHz high-speed I/O interfaces, and another bridge for the low-speed applications. The benefit is that the high speed I/O card does not have to wait for the low-speed application to finish its transfer. You will also have one bus running at 66 MHz and another slow bus running at 33 MHz.
