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The bridge does not do any cache snooping. The PCI bus is not responsible for snooping. If you think that snooping is required then you have to have your own cache controller on the PCI bus to do snooping. The bridge stores memory writes briefly but they continuously are written to the far side of the bridge. If you wish to flush the posted write buffers, your application should place an IO write or IO read command into the transaction queue. Memory writes initiated after that commands are executed after the IO transaction concludes.
The reference clock DC specifications and AC timing requirements are shown in the table below. More details can be found in "PCI Express Card Electromechanical Specification Revision 1.1", Chap 2.1.3.
