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Yes. Address space is reserved in multiples of 1 Mb for the prefetchable and non-prefetchable memory spaces.
When first powering the chip, either power the core voltage (3.3V) before powering Vio or allow 3.3V and 5V to rise together (as is normal for motherboard power supplies).
No, This is a commercial level grade part only.
The phase error is measured from the crosspoint of the input reference signals to the crosspoint of the output signals. For example, Pericom clock driver phase error is measured from CK and CK/ input pins to FBIN and FBIN/ pins. Therefore, all 4 probes of a typical oscilloscope are used.
A full detail explanation and product guidelines for memory modules and DDR applications can be found in our Applications section under Memory Modules.
This bridge is designed to Intel 21154BE capabilities (power management support at pin D11, 2KV ESD rating, 0.35 micron process, and more robust tolerances for 3.3V/5V power start up sequence.) The bridge also can be used in designs intended for 21154 versions AC, AE, and BC also.
The reference clock DC specifications and AC timing requirements are shown in the table below. More details can be found in "PCI Express Card Electromechanical Specification Revision 1.1", Chap 2.1.3.
MS1 (pin 106 for package MA-208) is pin R16 for the BGA 8150. It is normally connected to VSS. MS0 (pin 155 for package MA-208) is pin B14 for the BGA 8150. It is normally connected to VDD.
These are actually multiplexed pins. By default, we are compatible with the Intel 21150 solution, where pin 155 is VDD, and pin 106 is VSS. In future versions of this chip, changing the setting (pulled HIGH or LOW) on these pins will allow for future features. For now, these optional capabilities are reserved.
