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PI7C9X442SLB

PCI Express-to-USB 2.0 Swidge™ (PCIe Packet Switch + USB 2.0 Host Controller)
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Description

PI7C9X442SL PCI Express-to-USB 2.0 Swidge is a multi-functional device that combines the functionalities of PCI Express (PCIe) Packet Switch and PCIe-to-USB2.0 Bridge. The high-performance interconnect architecture of PI7C9X442SL is capable of fanning out from one PCIe x1 upstream port to two x1 downstream and four USB 2.0 ports. The device allows simultaneous access to multiple PCIe and USB devices from system host processor, and therefore expands the connectivity domain of the system. The high-speed and low-latency switch architecture offers 16 Gbps aggregated, full-duplex switching capacity for four integrated high-speed channels, one of which is used to bridge into four USB links. The device can operate at either store-and-forward or cut-through mode and support eight Traffic Classes (TCs) and one Virtual Channel (VC) with flexible and efficient resource management. The USB ports of the device can support all the available speeds including High-Speed (HS), Full-Speed (FS) and Low- Speed (LS). The PCIe-to-USB2.0 bridge function of the device is implemented by two types of host controllers, the Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI). There are one EHCI controller and two OHCI controllers residing in PI7C9X442SL. The EHCI controller handles High-Speed USB transaction while the OHCI controllers handle Full-Speed or Low-Speed USB transaction.

From the perspective of system model, the PCIe switch forwards posted, non-posted request and completion packets in downstream or upstream direction concurrently as if a virtual PCI bridge is in operation at each port. By visualizing the port as a virtual bridge, the switch can be logically viewed as two-level cascaded multiple virtual PCI-to-PCI bridges, where one upstream-port bridge sits upon all downstream-port bridges over a virtual PCI bus. In addition, three USB controllers are attached to one of the PCI Express downstream ports. During enumeration, each PCIe port is given a unique bus number, device number and function number that are logically formed as a destination ID. The USB host controllers are viewed as a multi-functional device by the bootstrapping procedures. The EHCI controller is assigned function #2 and the two OHCI controllers are assigned function #0 and #1, and all the controllers are assigned the same device number. The memory-map and IO address ranges are exclusively allocated to each port and USB host controller. After the software enumeration is completed, the transaction packets are routed to the dedicated PCIe port or USB host controller based on the embedded contents of address or destination ID.

For the PCIe switching function, the traffic from two PCIe downstream ports and one PCIe upstream port are exchanged on a peer-to-peer basis in the direction of either upstream or downstream. For the PCIe-to-USB bridging function, the four USB ports are first served in a host-centric manner by EHCI or OHCI host controllers, which then interface with the PCIe port to transfer packets to/from the upstream port through switch fabric. At High-Speed mode, all the USB ports are handled by ECHI controller with function #2. At Full-Speed and Low-Speed modes, USB port #1 and port #2 are handled by OHCI controller with function #0 and USB port #3 and port #4 are handled by OHCI controller with function #1. The Root Hub resides between the USB ports and host controllers and handles connection sessions from the host controller cores to USB ports.

Features

General Features

  • PCI Express to four USB 2.0 and two PCI Express downstream ports
  • Strapped pins configurable with optional EEPROM or SMBus
  • SMBus interface support
  • Industrial Temperature Range -40°C to 85°C
  • 128-pin LQFP 14mm x 14mm package

Industrial Compliance

  •  Compliant with PCI Express Base Specification Revision 1.1
  • Compliant with PCI Express CEM Specification Revision 1.1
  • Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2
  • Compliant with Advanced Configuration Power Interface (ACPI) Specification
  • Compliant with Universal Serial Bus Specification Revision 2.0 (data rate 1.5/12/480 Mbps)
  • Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
  • Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
  • Compliant with System Management (SM) Bus, Version 1.0

PCI Express Swidge

  • One x1 PCIe 1.1 upstream port and two x1 PCIe 1.1 downstream ports
  • Supports “Cut-Through” (default) as well as “Store and Forward” mode
  • 150 ns typical latency for packets routed through Swidge without blocking
  • Non-blocking full-wired switching capability at 16 Gbps provided for all 3 PCI Express ports and all 4 USB

2.0 ports

  • Advanced Power Saving

- Empty downstream ports are set to idle state to minimize power consumption
- Link Power Management
- Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power state
- Active state power management for L0s and L1 state
- PME# support in L2 state
- Device State Power Management
- Supports D0, D3Hot and D3Cold device power state
- 3.3V Aux Power support in D3Cold power state

  • Port Arbitration: Round Robin (RR), Weighted RR and Time-Based Weighted RR
  • Supports up to 256-byte maximum payload size
  • Programmable driver current and de-emphasis level at each PCIe port
  • Reliability, Availability and Serviceability

USB Host Controller

  •  USB Root Hub with 4 downstream facing ports shared by OHCI and EHCI host controllers
  • All USB downstream facing ports are able to handle high-speed (480 Mbps), full-speed (12 Mbps) and lowspeed (1.5 Mbps) transactions
  • PCI Express to USB bridging through PCI Express multi-functional core of PI7C9X442SL
  • Two OHCI host controllers for full-speed and low-speed and one EHCI host controller for high-speed
  • Programmable PHY parameters for each USB port
  • Operational registers of the USB Host Controller are directly mapped to PCI memory space

Product Specifications

Product Specs

Ports 3
Lanes 3
Power 0.55
Latency 150

Quality & Reliability

Quality Documentation

Process Qualification

Technical Documents

Additional Technical Documents are available upon request: 
Application information, Design tool model software, Design kits, Evaluation board, and Other technical documents

Request Documents

Orderable Part Number Status Package Temp Range ℃ Pb (Lead) Free Packing Buy from Distributor /
Contact Sales
PQR PDN Request
Qty. Carrier Samples Material Report (SGS)
PI7C9X442SLBFDE Active LQFP-128 -40 to 85 Yes 90 TRAY Samples SGS
PI7C9X442SLBFDEX Active LQFP-128 -40 to 85 Yes 1000 T/R Contact Sales Samples SGS

PCNs

Product Change Notices

PCN # Issue Date Subject
12-03 2012-23-01 Copper wire qualification for copper bondwire process for LQFP packages (FD128 and FA48) at Greatek assembly site.
14-19 2014-05-09 Add Nantong Fujitsu Microelectronics Co. Ltd. (NFME) as approved vendor listing for IC products in the QSOP, TSSOP, MSOP, QFN and LQFP packages.

FAQs

PCIe Switch FAQs

Can I change Pericom packet switch's PHY parameters by EEPROM or SMBus?

Yes, all Pericom's packet switches provide EEPROM/SMBus to change PHY parameters including Low Driver Current, High Drive Current, Driver Transmit Current, De-emphasis Transmit Equalization, Receive Termination Adjustment, Transmit Termination Adjustment and Receiver Equalization Level Control.

Can I change Pericom packet switch's PHY parameters by strapping pin options?

Only GreenPacket Family packet switches, PI7C9X20505GP, PI7C9X20508GP, provide strapping pin option to change PHY parameters to improve signal quality. The following strapping pins are available: HIDRV, LODRV, DTX[3:0], DEQ[3:0], RXEQCTL[1:0], RXTERMADJ[1:0] and TXTERMADJ[1:0].

Do Pericom's packet switches accept reference clock source which is different from the root complex?

Yes, Pericom Packet Switches support operation in asynchronous mode, in which the reference clock source of Pericom packet switch is different from that of the root complex. However, the deviation in the clock signals must be within +/- 300ppm.

Do Pericom's packet switches require the device driver?

Yes, Pericom's Packet Switches require the standard PCI-to-PCI Bridge device driver in order to work, which is built in most of the OS's. That is, most of the OS's automatically install the standard PCI-to-PCI Bridge device driver when a Pericom's packet switch is plugged in the system for first time.

Do Pericom's Packet Switches Support Industrial Temperature Range (-40oC to +85oC)?

"YES, please refer to the following application notes.

AN219 – GreenPacket PCI Express Packet Switch – Industrial Temperature Support 1.0

AN220 – PI7C9X20303SL-404SL Industrial Temperature Support

AN221 – PI7C9X20303ULA Industrial Temperature Support"

 

Does Pericom provide a Compatibility Test List for the Packet Switches?

Yes.  Please refer to the Application Note, "AN227 – Product Compatibility List" for the complete list.

Does Pericom provide the design kits for packet switches and what information is included in the kit?

Yes, Design Kits for Packet Switches are available and include datasheet, product brief, reference schematics, software tools, demo board user manual, design guideline, IBIS file and related application notes. The design kits can be requested from your distributer or Pericom FAE.

Does Pericom provide the power consumption for the Packet Switches?

Yes, power consumption information is included in the design kit.

Does Pericom's packet switches support Hot-Plug feature?

GreenPacket Family (PI7C9X20505GP, PI7C9X20508GP) provides full support for hot plug functions, including Power Indicator, Attention Indicator, Attention Button, Presence Detected Changes, Slot Power Enable Power Fault.  SlimPacket Family (PI7C9X20303SL, PI7C9X20404SL) and UltraLo Family PI7C9X20303UL only support Presence Detected Changes event.  EEPROM or the strapping pins are used to enable the hot plug feature.

Does Pericom's packet switches support Spread Spectrum Clock (SSC) Sources?

No, Pericom packet switch does not support SSC sources.

How do I configure the configuration registers of Pericom's packet switches?

Pericom's packet switches can be configured by the configuration registers. There are three methods for this purpose: configuration read/write, SMBus, and EEPROM. Configuration read/write and SMBus can access configuration registers on-line. However, SMBus can only access these registers below 100H offset. Configuration read/write method is required if you intend to access registers above 100H offset. EEPROM can change the default values of certain configuration registers. EEPROM content is auto-loaded to packet switch when power-on.

How do I know if a device has been obsoleted? I am unable of find the datasheet on the Pericom website.

If the datasheet is not found on Pericom's website, it is a strong indication that the part has been obsoleted. there are several ways to find out.  The first method would be to check on the Product Detail page for your particular product choice, if there are related PDN notices, they will show up on the tab, marked "PDNS".

Alternatively go Discontinuation Notices to search for the part number.

How do I use SMBUS interface of Pericom's packet switches?

Please refer to the application note, "PCIe Packet Switch SMBus Programming Guild 0.1c" for detailed information. Please set SMBus address using GPIO[7:5]. Otherwise, SMBus may not work due to unknown SMBus address.

How to implement MRL_PDCx/PRSNTx pin?

The pin is name "MRL_PDCx" in GreenPacket Family packet switches and "PRSNTx" in SlimPacket Family and UltraLo Family with the same function. MRL_PDCx/PRSNTx pin is used to indicate whether a device is present in the slot of downstream ports in express card interface implemention. When MRL_PDCx/PRSNTx is asserted high, it represents the device is present in the slot of downstream ports. Otherwise, it represents the absence of the device. If express card interface is not implemented, MRL_PDCx/PRSNTx should be connected to GND through a pull-down resistor.

Is EEPROM required in the implementation?

The implementation of EEPROM depends on specific application. Normally, a packet switch is fully functional without EEPROM. However, in certain applications, EEPROM is needed to change certain default values of configuration registers. We recommend keeping the EEPROM footprint and circuitry just in case.

Is there a replacement for an obsolete part?

Not all obsolete parts will have a direct replacement. However, we recommended that you contact your regional sales office.

What are the PHY parameters?

In order to meet the different application needs, the driving current and equalization of each transmitting channels can be adjusted individually using strapped pins (GreenPacket Family) and EEPROM (GreenPacket/SlimPacket/UltraLo Family). The driver current of each channel is set to 20mA in default mode without pins being strapped. To change the current value, the user can strap the pins/EEPROM either for nominal value (HIDRV, LODRV) or actual value (DTX [3:0]), which is a scaled multiple of Inom. The following tables illustrate the possible transmitted current values the chip provides.

What are the reasons that a Pericom's packet switch can not detect the plugging in of an endpoint in embedded system?

It is most likely that the boot code of the embedded system does not initialize Pericom's packet switch. The packet switch needs to be initialized in order to work normally. The packet switch is initialized by BIOS on x 86 systems and by the boot code on embedded system.

What are the reasons that Pericom's packet switch on an evaluation board can not detect an express card or a mini-pcie device?

The evaluation board of a Pericom's packet switch only provides the PCIe x1 slot on the downstream ports. Customers need an adapter they would like to plug in the express card or mini-pcie device. When the PRSNT# pin of the adapter is floating, the express card or mini-pcie card can not be detected.

What are the types of jitter?

There are several types of jitter, but the main ones are: cycle-to-cycle jitter, period jitter, half period jitter, and peak-to-peak jitter. Jitter terminology can be found in AB36: Jitter Measurement Techniques at Application Brief No. 36 or Application Note No. 27.

What is Surprise Hot Removal Function? Do Pericom's packet switches support it?

Surprise Hot Removal function allows unplugging of express card without prior notification. All Pericom's packet switches support this function. All downstream ports of SlimPacket Family and UltraLo Family packet switches support the surprise hot removal function. Only Port 1 and Port 2 of GreenPacket Family packet switches support this function. That is, only Port 1 and Port 2 of GreenPacket Family packet switches can implement the express card interface.

What is the lead finish for Pericom products? What about lead-free?

All Pericom's products that are not lead-free are composed of 85% Sn and 15% Pb. For lead-free products, they are composed of 100% matte Sn. Lead-free products are marked and ordered with the letter "E" suffix at the end of the part number.

What is the requirement of the reference clock of Pericom's packet switches?

The reference clock DC specifications and AC timing requirements are shown in the table below. More details can be found in "PCI Express Card Electromechanical Specification Revision 1.1", Chap 2.1.3.

 

Where can I find Mean Time Before Failure (MTBF) or Failures In Time (FIT) values for Pericom products?

FIT and MTBF data can be found at Pericom's Quality webpage.

Where can I find the information on your Pb-free and "Green" packaging?

Lead (Pb)-Free and Green information can be found on individual datasheets or Pb-Free & Green Page.

Why is AC-Coupling required in the reference clock input pairs?

The reference clock input pins connect to external 100MHz differential clock. The signal must match to LVPECL or HCSL spec.  A 100nF capacitor should be placed between the clock source and the packet switch. The purpose of this capacitor is to achieve AC coupling. This AC Coupling ensures the Packet Switch is compatible with the differential clock signals regardless the type of the clock. The input clock signals must be delivered to the clock buffer cell through an AC-coupled interface so that only the AC information of the clock is received, converted, and buffered. Please refer to the application note, "Express Interface AC-Coupling Application Note", in the design kit for more details.

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