PI7C9X442SL

Description

PI7C9X442SL PCI Express-to-USB 2.0 Swidge is a multi-functional device that combines the functionalities of PCI Express (PCIe) Packet Switch and PCIe-to-USB2.0 Bridge. The high-performance interconnect architecture of PI7C9X442SL is capable of fanning out from one PCIe x1 upstream port to two x1 downstream and four USB 2.0 ports. The device allows simultaneous access to multiple PCIe and USB devices from system host processor, and therefore expands the connectivity domain of the system. The high-speed and low-latency switch architecture offers 16 Gbps aggregated, full-duplex switching capacity for four integrated high-speed channels, one of which is used to bridge into four USB links. The device can operate at either store-and-forward or cut-through mode and support eight Traffic Classes (TCs) and one Virtual Channel (VC) with flexible and efficient resource management. The USB ports of the device can support all the available speeds including High-Speed (HS), Full-Speed (FS) and Low- Speed (LS). The PCIe-to-USB2.0 bridge function of the device is implemented by two types of host controllers, the Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OHCI). There are one EHCI controller and two OHCI controllers residing in PI7C9X442SL. The EHCI controller handles High-Speed USB transaction while the OHCI controllers handle Full-Speed or Low-Speed USB transaction.

From the perspective of system model, the PCIe switch forwards posted, non-posted request and completion packets in downstream or upstream direction concurrently as if a virtual PCI bridge is in operation at each port. By visualizing the port as a virtual bridge, the switch can be logically viewed as two-level cascaded multiple virtual PCI-to-PCI bridges, where one upstream-port bridge sits upon all downstream-port bridges over a virtual PCI bus. In addition, three USB controllers are attached to one of the PCI Express downstream ports. During enumeration, each PCIe port is given a unique bus number, device number and function number that are logically formed as a destination ID. The USB host controllers are viewed as a multi-functional device by the bootstrapping procedures. The EHCI controller is assigned function #2 and the two OHCI controllers are assigned function #0 and #1, and all the controllers are assigned the same device number. The memory-map and IO address ranges are exclusively allocated to each port and USB host controller. After the software enumeration is completed, the transaction packets are routed to the dedicated PCIe port or USB host controller based on the embedded contents of address or destination ID. 

For the PCIe switching function, the traffic from two PCIe downstream ports and one PCIe upstream port are exchanged on a peer-to-peer basis in the direction of either upstream or downstream. For the PCIe-to-USB bridging function, the four USB ports are first served in a host-centric manner by EHCI or OHCI host controllers, which then interface with the PCIe port to transfer packets to/from the upstream port through switch fabric. At High-Speed mode, all the USB ports are handled by ECHI controller with function #2. At Full-Speed and Low-Speed modes, USB port #1 and port #2 are handled by OHCI controller with function #0 and USB port #3 and port #4 are handled by OHCI controller with function #1. The Root Hub resides between the USB ports and host controllers and handles connection sessions from the host controller cores to USB ports.

Features

General Features

• PCI Express to four USB 2.0 and two PCI Express downstream ports
• Strapped pins configurable with optional EEPROM or SMBus
• SMBus interface support
• Industrial Temperature Range -40°C to 85°C
• 128-pin LQFP 14mm x 14mm package

Industrial Compliance

•  Compliant with PCI Express Base Specification Revision 1.1
• Compliant with PCI Express CEM Specification Revision 1.1
• Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2
• Compliant with Advanced Configuration Power Interface (ACPI) Specification
• Compliant with Universal Serial Bus Specification Revision 2.0 (data rate 1.5/12/480 Mbps)
• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
• Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
• Compliant with System Management (SM) Bus, Version 1.0

PCI Express Swidge

• One x1 PCIe 1.1 upstream port and two x1 PCIe 1.1 downstream ports
• Supports “Cut-Through” (default) as well as “Store and Forward” mode
• 150 ns typical latency for packets routed through Swidge without blocking
• Non-blocking full-wired switching capability at 16 Gbps provided for all 3 PCI Express ports and all 4 USB

2.0 ports

• Advanced Power Saving

- Empty downstream ports are set to idle state to minimize power consumption
- Link Power Management
- Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power state
- Active state power management for L0s and L1 state
- PME# support in L2 state
- Device State Power Management
- Supports D0, D3Hot and D3Cold device power state
- 3.3V Aux Power support in D3Cold power state

• Port Arbitration: Round Robin (RR), Weighted RR and Time-Based Weighted RR
• Supports up to 256-byte maximum payload size
• Programmable driver current and de-emphasis level at each PCIe port
• Reliability, Availability and Serviceability

USB Host Controller

•  USB Root Hub with 4 downstream facing ports shared by OHCI and EHCI host controllers
• All USB downstream facing ports are able to handle high-speed (480 Mbps), full-speed (12 Mbps) and lowspeed (1.5 Mbps) transactions
• PCI Express to USB bridging through PCI Express multi-functional core of PI7C9X442SL
• Two OHCI host controllers for full-speed and low-speed and one EHCI host controller for high-speed
• Programmable PHY parameters for each USB port
• Operational registers of the USB Host Controller are directly mapped to PCI memory space