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PCIe / PCI Bridges

PCIe PCI Bridge

PCIe-to-PCI / PCIX Bridge product capable of Forward or Reverse bridging are offered by Pericom. “Forward” (PCIe-to-PCI/PCIX) mode provides an effective turn-key bridging solution between PCI Express Host on the primary side and PCI/PCIX Peripheral Devices as the secondary interface. The “Reverse” (PCI / PCIX-to-PCIe) mode offers the Reverse Bridging capability, proven effective in bridging new PCI Express End Point Devices to legacy PCI Host CPUs with minimal impact to existing PCI Hardware/Software investment. Pericom’s performance-tuned PCIe-to-PCI / PCIX Bridges are specifically designed for a variety of applications and platforms: PC/Notebook systems, PCIe add-in cards, Compact PCI and PCIe systems, Multi-Function or Enterprise Printers, Network Routers and Switches, Industrial PC’s and Security/Video Surveillance Systems. As an active member and participant of PCI-SIG®, PICMG®, and ASI SIG Plugfest, all Pericom PCIe-to-PCI/PCIX Bridge Products are fully qualified on PCISIG Integrator’s list.

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PCIe / PCI Bridges Details

Pericom offers the following bridge solutions:

  • PCI to PCI
  • PCI-X to PCI-X
  • PCIe to PCI
  • PCIe to PCI-X
  • PCIe to UART I/O Bridge

Bridge Benefits and Features

  • PCI & PCI-X Bridges allow add-on devices in a system
  • Creates a separate secondary bus
  • Permits more devices or “loads” to be added to the system
    • Allows for more slots for adapter cards in a system
    • Allows for multiple devices on a line card or add-in card

Intel Compatible PCI-to-PCI Bridges

  • Drop-in replacements for popular Intel 2-port devices
  • Extended commercial temperature range (0 °C to 85 °C)

Enhanced PCI-to-PCI Bridges

3-port products feature:

  • One primary and two secondary buses
  • Ideal for redundant applications
  • Used for traffic isolation and offer unique peer-to-peer mode
  • Industrial temperature range

PCIe to PCI Reversible Bridge

Non-Transparent Mode for PCIe to PCI bridge:

  • Supports isochronous data streaming
  • Dual priority modes small package: 12 x 12 PBGA 160-pin
  • Reverse mode option – outstanding reverse mode performance
  • High output drivers – can drive 8 PCI devices across connectors
  • Industrial temperature range

PCI Express® to PCI & PCI-X Reversible Bridge

Transparent and Non-Transparent Mode:

  • Virtual isochronous support
  • Large package: 17 x 17 PBGA 256-pin
  • Fully reversible
  • Industrial temperature range

PCI Express® to UART

Support 2, 4, or 8 high-performance 16C950 UART ports in a single chip:

  • Fully software compatible with 16C550-type device drivers
  • 128-byte transmit and receive FIFO
  • Flexible clock pre-scaler from 4 to 46
  • Data framing sizes: 5, 6, 7, 8 and 9
  • Baud rate up to 15 Mbps in asynchronous mode and 62.5 Mbps in synchronous mode
  • Supports up to 256-byte maximum payload size
  • 0.7W-2 port, 0.8W-4 port, 0.9W-8 port typical
  • Commercial temperature range 0 °C to 70 °C
  • Package: Available in 12 x 12 mm, 160-pin LFBGA and 14 x 14 mm, 128-pin LQFP, Pb-free and 100% Green

PCIe / PCI Bridges FAQs

Any recommendations for off the shelf utilities to help tune our bridge application?

Yes. Under any Windows OS, one excellent shareware tool is at www.PCItree.de Follow the install directions in the pt_userg.html file. Changes made with this tool are not permanent, so tuning bridge registers is safe and easy.

 

Any special attention needed for the 7300D placed into a very old system?

The BIOS date is important. The PI7C7300D bridge counts 225 PCI clocks from the de-assertion of P_RESET# to the first allowable PCI config cycle, per PCI Spec 2.2**. This is 33 million clocks, about 1 full second at 33 MHz. For BIOS made according to Intel/Microsoft AC97 ("green PC") specification, this 1 second (at 33 MHz) delay is not a problem. But for older BIOS standard, this will block BIOS from enumerating the PCI devices on the secondary PCI bus and thus they have no resources assigned. Since DOS uses the BIOS for PCI enumeration (enumerate == "detect and assign resources"), a motherboard BIOS older than 1996 years might not detect and allocate resources to devices behind the bridge. When plug and play OS loads (many seconds later), then its first enumeration of the computer will detect our bridge (and the devices behind it). Thus Windows 9x and Windows ME OS will detect the bridge, as will any motherboard modern enough to run Windows 2000 or XP. **This is found at page 128, section 4.2.3.2 "Timing Parameters" PCI specification 2.2 table 4-6, Trhfa "RST# High to First Configuration Access". A workaround exists: Place two diodes, P_RESET# to S1_REQ#6 And P_RESET# to S1_REQ#7 so that as P_RESET# is low the internal arbiter senses S1_REQ#6 and S1_REQ#7 low. The diode blocks normal REQ# assertion from resetting the system, but allows P_RESET# to pull low the corresponding S1_REQ#.

Are Linux drivers available for the 8150 PCI Bridge?

The bridge uses the generic PCI-PCI bridge driver already part of Linux kernel 2.2; there is no need for a Pericom specific driver.

 

Are Linux drivers available for the PI7C7300D?

The PI7C7300D pci-pci bridge will appear to your OS as two standard PCI-PCI bridges. We require no added device driver for Linux kernel 2.2 and higher; our test under Linux (Red Hat 7.0 on Intel PC) locates, configures, and runs devices behind the bridge.

 

 

 

 

Are PCI ports of PI7C9X110 capable of 25MHz and 50MHz?

Yes, 25MHz and 50MHz clock signals have to be supplied to the PCI ports.

Are PCI ports of PI7C9X111 capable of 25MHz and 50MHz?

Yes, 25MHz and 50MHz clock signals have to be supplied to the PCI ports.

Are there any other documents I can refer to in addition to the datasheet to clarify the questions I have?

For more information, please refer to the following specifications:

 • PCI Express Base Specification

• PCI Express Card Electromechanical Specification

• PCI Local Bus Specification

• PCI Express to PCI/PCI-X Bridge Specification

Can I float inputs such as the REQ# signals, MSK_IN or S_CFN_L?

No, Inputs should not be left floating. Pull DOWN pin 23 (S_CFN_L) secondary bus arbiter select. Pull DOWN pin 126 MSK_IN to turn on all the secondary bus clocks without programming through GPIO. REQ signals should have pull-Ups to Vio. See Application Notes 55 , 58 , 60 for further details.

 

Can I have the two busses work at different frequencies?

Yes, you can have the secondary bus running at similar speed at the primary, or you can have the secondary bus running at half the speed of the primary bus. So, if the primary bus is running at 66 MHz then the secondary bus can be running at 33 MHz or 66 MHz. This is controlled by Config66 and s_m66en signals. If both are high, then the secondary will run at the same speed as the primary bus. If either one of them is low, then the secondary bus will run at half the speed of the primary bus.

 

Can I plug this board in a PCI-X slot?

Yes you can, the PCI-X specification is backward compatible with this bridge, and it will work at 66 MHz speed.

Can I select 33 MHz operation on the Primary, even with the Primary clock being 66 MHz?

A 66 MHz bus normally drops to 33 MHz when the M66EN signal is driven low. So, you could bring down the primary bus to 33 MHz by tying or pulling low the P_M66EN signal, if that is your wish. More importantly, some other card might do this to you if it is designed for 33 MHz but plugged into a normally 66 MHz bus.

 

Can I supply 1.0V power to VTT to reduce the types of the supply voltages?

Yes, this can be done. In fact, the evaluation board was designed this way.

Can memory mapped address space for a secondary bus device be larger than 1 MB?

Yes. Address space is reserved in multiples of 1 Mb for the prefetchable and non-prefetchable memory spaces.

 

Can the primary and secondary buses of the 8152 be set to different clock frequencies?

No

 

 

No
Can the secondary bus run at a higher speed than the primary bus?

No, the secondary bus runs at equal or half the frequency of the primary bus.

 

Can this work in a 64-bit slot?

Yes, you can plug it in a 64-bit slot. The system will automatically resize the slot to 32-bit, all transfers will occur at 32-bit data width.

Can unused secondary clock s_clk[1..4] be unconnected or do I need to disable them by programming bridge registers?

Tie one clock to S_CLKIN (pin 51). The other unused clocks can be unconnected.By default all the clocks are enabled; unused clocks can also be turned off at the Secondary Clock Control Register (configuration register offset 68h, bits 8:0).

 

 

Tie one clock to S_CLKIN (pin 51). The other unused clocks can be unconnected.By default all the clocks are enabled; unused clocks can also be turned off at the Secondary Clock Control Register (configuration register offset 68h, bits 8:0).
Can unused secondary clock s_clk[1..9] Be unconnected or do I need to disable them by programming the clock mode (using GPIO and MSK_IN)?

Tie one clock to S_CLKIN (pin 21 for the FQFP 208 pin package). The other unused clocks can be unconnected; connect MSK_IN (pin 126) low to skip using the GPIO clock programming circuit and the unused clock outputs can be left no connect.

 

Do designers make use of a pie filter or does a simple decoupling scheme using say, 0.1uF and 22uF Caps, work sufficiently?

Either could work, so long as the total decoupling capacitance is provided. Our general guideline is to decouple power entering the board with .1 and 10uF caps and again for safety at the four corners of the bridge IC with .1, .01, and 10uF caps.

 

Do I need a hot-swap controller to design Hot -Swap hardware?

Yes, a Hot swap controller is needed to ramp up the power as needed. It will also shut down if there is something wrong and there is too much current flowing through the Vcc planes.

 

Do I need to connect center pad (pin 129) on the bottom of the IC?

Yes, the center pad on the bottom is a ground pad, and must be connected to the ground. It is recommended that a few vias be designed in the board layout for adequate connection.

Do I need to write a driver in order to use a PCI-PCI bridge?

Our bridge doesn't need a Pericom specific device driver. At the Windows 2000/XP level, the generic pci-pci bridge driver pci.sys is all that is needed, which comes with every windows. Linux (Red Hat 7) supported our bridge with no driver from us, using a default pci-pci bridge driver.

 

 

Our bridge doesn't need a Pericom specific device driver. At the Windows 2000/XP level, the generic pci-pci bridge driver pci.sys is all that is needed, which comes with every windows. Linux (Red Hat 7) supported our bridge with no driver from us, using a default pci-pci bridge driver.
Do the P_Vio / S_Vio pins control the output voltage or the output driver levels?

P_Vio and S_Vio pins at our bridges control "output driving strength", which is related to current not voltage levels. The V/I curves between 3.3 V signaling and 5V signaling spec differ, and our exact pullup and pulldown curves can be viewed from our IBIS model, where "high drive" is with (P/S)_Vio input of 5V and "low drive" is (P/S)_Vio input of 3.3V.

 

Do we need to configure any of the registers to make this bridge function?

Generally the system BIOS (in non plug and play environment) will configure the bridge -- that is, assign PCI bus number, enumerate (detect and assign address ranges) devices on the secondary buses, and update the memory ranges assigned to each bus. The OS does this for plug and play systems. Once this much configuring is done, the bridge can forward transactions in either direction without further Pericom-specific drivers being needed. For the Windows and Linux environments the bridge uses the generic bridge driver already part of the OS kernel.

 

Do we need to mount a heat sink for 66 MHz applications?

Maybe. You'll want to determine temperature at the die junction, but that involves first knowing the power, the thermal resistance (theta Ja) of the part, and the ambient air temperature. Power = Vcc * Icc. Peak traffic generates the following current at the bridge: Peak ICC @ 3.6V Vcc. 5 MHz 61 mA (all 3 buses at 5 Mhz). 33 MHz 310mA (all 3 buses at 33 MHz). 66 MHz 780 mA (all 3 buses at 66 MHz). Theta Ja for the NA272 package is 27.55 C/W. Tj = Temp_Air + Power[Theta Ja]. See Packaging Mechanicals for more information.

 

Do you have an application note on FET isolation that you recommend?

The best and most recent app note for hot insertion *Switches* is Application Note 52 .

 

Do you have any decoupling recommendation and other schematics and Layout guidelines?

Yes, all these guidelines are available in the Hardware implementation Guides. All relevant Application Note/Briefs are available under the APPLICATION NOTES tab on the PRODUCT DETAIL PAGE for each product in the FINDER tool. Please refer to Bridges

Hardware Implementation Guide for PI7C8150 PCI-PCI Bridge

Hardware Implementation Guide for PI7C8152

Hardware Implementation Guide for PI7C8154.

 

Do you have any decoupling recommendations and any other schematics and layout guidelines for this device 7300D?

Yes, all these guidelines are available in the Schematics and Layout guidelines for the 7300. See Application Note 44.

 

Do you have any decoupling recommendations and other schematics and Layout guidelines?

Yes, all these guidelines are available in the Hardware implementation Guide for the PI7C8154. See Application Note 60

 

Does it support both Non-Transparent Mode and Transparent Mode?

The 7300D and 815x family of bridges are transparent bridges.

 

Does PI7C9X110 support 5V PCI devices on the PCI interface?

Yes, PI7C9X110 supports 5V PCI devices on the PCI interface.

Does PI7C9X110 support 64-bit address space?

Yes, PI7C9X110 supports 64-bit address space.

Does PI7C9X110 support Burst Transmission mode?

Yes, PI7C9X110 supports Burst Transmission mode.

Does PI7C9X110 support Hot-Plug function?

Yes, PI7C9X110 supports Hot-Plug function, but only the system supports with compatible hardware, software, and connectors. Please refer to the following specification for details:

• PCI Hot-Plug Specification

• PCI Standard Hot-Plug Controller and Subsystem Specification

Does PI7C9X110 support Industrial Temperature range?

Yes, PI7C9X110 supports Industrial Temperature range (-40oC to 85oC).

Does PI7C9X110 work without EEPROM?

Yes, PI7C9X110 works without EEPROM. The device uses the default values in the registers. If EEPROM is available during power-up, the device loads the values from EEPROM after validating the content, and over-writes the default values in the registers. After initial power-up, the register values can be written via PCI/PCIe configuration registers.

Does PI7C9X111 require external PCI clock source in Forward mode?

PI7C9X111 has internal clock source available for use shown in the table below. External clock source is not needed. If the system needs to use external clock source, please refer the Clock Scheme section of the datasheet.

Does PI7C9X111 support 5V PCI devices on the PCI interface?

Yes, PI7C9X111 supports 5V PCI devices on the PCI interface.

Does PI7C9X111 support 64-bit address space?

Yes, PI7C9X111 supports 64-bit address space.

Does PI7C9X111 support Hot-Plug function?

Yes, PI7C9X111 supports Hot-Plug function, but only the system supports with compatible hardware, software, and connectors. Please refer to the following specification for details:

• PCI Hot-Plug Specification

• PCI Standard Hot-Plug Controller and Subsystem Specification

 

Does PI7C9X111 support Industrial Temperature range?

Yes, PI7C9X111 supports Industrial Temperature range (-40oC to 85oC).

Does PI7C9X111 work without EEPROM?

Yes, PI7C9X111 works without EEPROM. The device uses the default values in the registers. If EEPROM is available during power-up, the device loads the values from EEPROM after validating the content, and over-writes the default values in the registers. After initial power-up, the register values can be written via PCI/PCIe configuration registers.

Does PI7C9X111SL support Burst Transmission mode?

Yes, PI7C9X111SL supports Burst Transmission mode.

Does PI7C9X130 support 5V PCI devices on the PCI interface?

Yes, PI7C9X130  supports 5V PCI devices on the PCI interface.

Does PI7C9X130 support 64-bit address space?

Yes, PI7C9X130 supports 64-bit address space.

Does PI7C9X130 support Burst Transmission mode?

Yes, PI7C9X130 supports Burst Transmission mode.

Does PI7C9X130 support Hot-Plug function?

Yes, PI7C9X130  supports Hot-Plug function, but only the system supports with compatible hardware, software, and connectors. Please refer to the following specification for details:

• PCI Hot-Plug Specification

• PCI Standard Hot-Plug Controller and Subsystem Specification

Does PI7C9X130 support Industrial Temperature range?

Yes, PI7C9X130 supports Industrial Temperature range (-40°C to 85°C).

Does PI7C9X130 work without EEPROM?

Yes, PI7C9X130 works without EEPROM. The device uses the default values in the registers. If EEPROM is available during power-up, the device loads the values from EEPROM after validating the content, and over-writes the default values in the registers. After initial power-up, the register values can be written via PCI/PCIe configuration registers.

Does the 8150 have any power ramping requirements?

When first powering the chip, either power the core voltage (3.3V) before powering Vio or allow 3.3V and 5V to rise together (as is normal for motherboard power supplies).

 

Does the 8152 have any power ramping requirements?

When first powering the chip, either power the core voltage (3.3V) before powering Vio or allow 3.3V and 5V to rise together (as is normal for motherboard power supplies).

 

Does the bridge implement cache snooping?

The bridge does not do any cache snooping. The PCI bus is not responsible for snooping. If you think that snooping is required then you have to have your own cache controller on the PCI bus to do snooping. The bridge stores memory writes briefly but they continuously are written to the far side of the bridge. If you wish to flush the posted write buffers, your application should place an IO write or IO read command into the transaction queue. Memory writes initiated after that commands are executed after the IO transaction concludes.

Does the bridge support industrial temperature?

No, This is a commercial level grade part only.

 

Does the internal arbiter rotate between S1 and S2 or are they arbitrated independently? Do both buses need to be idle before a transaction can start?

Each of the three buses {Primary, secondary S1, secondary S2} are independent and thus each will be arbitrated separately, regardless of activity or idle state on another bus.

Does the PCIe bridge's PCIe port support asynchronous clock source?

Yes, the PCIe bridge supports asynchronous differential 100Mhz clock sources on two sides of the PCIe port, provided the PCIe device on the other side supports asynchronous clock sources too. It should be noted that not all PCIe devices support asynchronous clock sources.

f I supply 66 MHz to the Primary Clock input, can I choose between 33 MHz or 66 MHz on the Secondary buses?

Yes, depending on the state of signal S_M66EN, when the primary Clock is 66 MHz you can have both, either, or neither secondary bus set to the same speed (S_M66EN = high) or half speed of the primary bus (S_M66EN = low).

 

For the 66 MHz enable signals, do they only affect the chip during startup? Is this pin looked at by the PI7C7300 after initialization?

The M66EN signals are used directly to the control logic. We do not use the M66EN for strapping, (and thus the M66EN signals are "live" at all times).

 

GPIO support for PI7C8154A?

GPIOs exist in the PI7C8154A. Please check Configuration register offset 64H in the data sheet.

 

Hot-Insertion: Is it guaranteed "Safe" to Remove or Insert a module containing the PI7C7300D device from a powered up "live" system?

The PI7C7300D is "hot-swap friendly", which essentially means it can interface to a hot-swap power controller. But by itself cannot withstand Vcc=0V and live signals at the I/O pins -- in this mode, current will flow through our bridge. Therefore, if ever there is a possibility of this happening, we require a hot-swap power controller and switches for isolation. If you do not need to pre-charge your switched signals, then the less costly  or PI3C32X245 switches are appropriate for the signal switches. Most of our customers use this switch in their applications.

 

How can I increase performance on this chip?

Normally, most motherboards set the Cache Line Size of the motherboard primary PCI bus (i.e. system North Bridge) to 8, with some of the newer ones choosing 16. At boot time, the system BIOS copies this value to our bridge CLS register. The number is small where little bursting is expected; but smaller burst lengths decrease available PCI bandwidth. The tradeoff is that small bursts have smaller latency, that is, less impact on other devices waiting to use the PCI bus. This said, in general the best possible performance occurs with our bridge set to cache line size “00”, which allows read and write bursting to 4Kb address boundaries and prefetch behavior identical to cache line size 16. The best possible latency happens with smaller CLS values in the range of 4 to 8.

 

How compatible is your part to the 21152? Will Intel drivers work with this device?

The PI7C8152A was intended to be a pin compatible drop-in replacement to the Intel 21152. The drivers that currently work for the Intel device will function with our device as well. The PI7C8152A does not require any external drivers, but instead utilizes the embedded drivers in Windows. The only issue that may come up is that if your software is looking specifically for the Intel device and vendor ID's, it will need to be modified. The PI7C8152A has an added feature, it can work at 66 MHz. our device ID and vendor ID are different from Intel's.

How compatible is your part to the Intel 21150? Will Intel drivers work with this device?

The PI7C8150B was intended to be a pin compatible drop-in replacement to the Intel 21150. The drivers that currently work for the Intel device will function with our device as well. The PI7C8150B does not require any external drivers, but instead utilizes the embedded drivers in Windows. The only issue that may come up is that if your software is looking specifically for the Intel device and vendor ID's, it will need to be modified. Our device and vendor ID's are different from Intel's.

How do I know if a device has been obsoleted? I am unable of find the datasheet on the Pericom website.

If the datasheet is not found on Pericom's website, it is a strong indication that the part has been obsoleted. there are several ways to find out.  The first method would be to check on the Product Detail page for your particular product choice, if there are related PDN notices, they will show up on the tab, marked "PDNS".

Alternatively go Discontinuation Notices to search for the part number.

How do we connect the reserved Pins?

RESVD (pin 127 in package MA-208) is at J14, leave this as NC (no connect),RESVD (pin 128 in package MA-208) is at J16, leave this as NC (no connect).

 

How do you set non-prefetchable read mode?

Non-prefetchable read transactions use single DWORD data phases. Section 3.6.3 “Read Prefetch Address Boundaries” shows that Memory Read Line and Memory Read Multiple commands implicitly prefetch. Memory Read commands behave differently: For Downstream memory read commands (i.e. target device is on the secondary PCI bus), program config address 20h with your memory mapped I/O range (i.e. non-prefetch) and for config address 24h the prefetch base address needs to be *higher* than the prefetch limit address. Example: [Config register offset 24] write 0000FFFF (which will read back as 0000FFF0 as the last byte is RO) [Config register offset 28] defaults to 00000000 so the upper 32-bits for prefetch base and prefetch limit line up . Upstream defaults to PREFETCHABLE due to config offset 40h bit 4 = 0 after reset. Write offset 40h bit 4 to be "1" to turn off upstream prefetching.

 

How does the bridge know to forward a transaction to the correct bus? Will PCI traffic on either secondary bus to the other secondary bus of the same bridge IC impact traffic at the primary bus?

At boot up, the BIOS probes each PCI bus to look for PCI devices that have memory or IO requirements. When finished reading all possible device numbers, the PCI Bridge, which owns that PCI bus, has memory ranges programmed for (I/O, non-prefetchable memory, and prefetchable memory). This continues until BIOS has found all PCI buses and all devices on those buses. After that, whenever a PCI transaction happens, the bridge checks the address of the target against the memory RANGE programmed at each bus within the BRIDGE configuration register. If the initiator is on a secondary bus and the target address is outside the ranges (start address until end address) of all the memory and I/O address registers, the transaction is forwarded to the primary PCI bus for some other device to claim it. If the initiator is on the primary PCI bus and the target address does not decode to one of the address ranges in config register 0 (for bus S1) or config register 1 (for bus S2), then the bridge does not claim the transaction. In both cases, the CPU is not used.

 

How large are the posted Write FIFOs on this bridge?

This bridge has two separate posted write FIFOs or buffers, each with 32 DWords (128 bytes) and one per side (i.e. one on the primary PCI port and one on the secondary PCI port). These two FIFOs are used to store all memory write and memory write invalidate transactions going through the bridge. The bridge will continue to store data (until an internal boundary is met) as long as there is room in the FIFO. Once the bridge has one entry, it will start to empty the FIFO on the other side. For the PI7C8154 , there are two posted write buffers of 32 DWords in each direction in order to accommodate the 64-bit data path (thus 256 bytes of data in each direction).

 

How large are the Read FIFOs on this bridge?

This chip has two 128-bytes of delayed transaction buffers, one FIFO on each side. Read transactions are treated as delayed transactions and are stored in this FIFO. When the bridge receives a Memory read request, it will continue to prefetch data until the FIFO is full, or it reaches an internal boundary if this transaction is prefetchable. If this is not prefetchable, like I/O read, configuration read, or a non prefetchable memory read cycle, then the bridge will read the requested read data only. The PI7C8154A is similar except it has two 32 Dword FIFOs in each direction in order to accommodate the 64 bit data path (thus 256 bytes of data in each direction).

 

How long has the 8154 been in production?

The PI7C8154A was released in November 2002.

 

How should I connect pull-ups? To which voltage level?

We recommend using Vio for pull-ups.

 

How should JTAG signals be handled if JTAG is not used?

TRST# signal should be pulled down through a 330ohm resistor.

TMS and TDI signals should be pulled up through a 5.1k-ohm resistor.

TCK signal should be pulled down through a 5.1k-ohm resistor.

TDO signal should be left floating.

 

How should PCIXCAP and PCIXUP signals be handled?

Please refer to the application circuit diagram below based on the PCI bus requirement.

How should PRSNT1# and PRSNT2# pins in PCI slot be handled?

PRSNT1# and PRSNT2# pins in PCI slot are used by add-in card to indicate the presence status. On the Motherboard, they should be pulled up. On the add-in card, they should be configured based on the card's power status.

 Please refer to PCI Specification 4.4.1 for more information.

 

How should the decoupling capacitor be placed in TN/TP pins of PCIe port?

Per PCI Express Specification, the egress signals of PCIe port require 0.1μF decoupling capacitor to be placed. Therefore, the PCIe bridge's TN/TP pins require 0.1μF decoupling capacitor. Similarly, the egress signals of the PCIe port of the connected PCIe device require 0.1μF decoupling capacitor.

How should the PCI device's IDSEL signal be connected?

Forward mode:

the PCIe bridge's IDSEL should be grounded through a 1k ohm resistor. IDSEL signals of the connected PCI devices should be connected to one of AD16-AD31 signals per PCI Specification. The AD signal used determines the PCI device's device number. Please refer to the table below:

Reverse mode:

IDSEL signal should be connected to the IDSEL signal of the PCI controller on the CPU side.

How should the REFCLKN/REFCLKP pins of PCIe port of the PCIe bridge be connected?

The REFCLKN/REFCLKP pins require 0.1μF decoupling capacitor. In testing the signals, only AC characteristics should be tested to comply with PCIe Specification. There is no requirement to testing DC characteristics.

How to reset the bridge by software?

There are two reset bits:1- secondary reset -- bit 22 offset 3c Hex This bit will reset the secondary interface signals and the FIFOs.2- Chip reset -- bit 8 offset 40 Hex .This bit will reset the entire chip, primary, secondary bus and the FIFOs as well as the internal registers.

If EEPROM is not used in the system, how should be done to the SMBCLK/SCL and SMBDATA/SDA pins?

Per PCI Specification 4.3.3, these two pins should be pulled up. The recommended value of pull-up register is 5.1k-ohm.

If INTA_L, INTB_L, INTC_L, and INTD_L signals are not used, can they be left floating?

These interrupt signals must be pulled up through a 5.1k-ohm resistor whether they are used or not.

If LOCK_L and PME_L signals are not used, can they be left floating?

LOCK_L and PME_L signals must be pulled up through a 5.1k-ohm resistor whether they are used or not.

If there are multiple PCI devices connected, how should they be connected to INTA#, INTB#, INTC#, and INTD# signals?

INTA#, INTB#, INTC#, and INTD# signals are shared by multiple PCI devices in a daisy chain. It depends on which AD signal is used on IDSEL pin. Please refer to the mapping table below, and PCI Specification 2.2.6 for more information.

In Forward mode, INTA#,INTB#, INTC#, INTD# of the PCIe bridge are equivalent to the interrupt pins on the Motherboard side in the table below - IRQW, IRQX, IRQY, and IRQZ. INTA#,INTB#, INTC#, INTD# on the PCI bus of the PCIe bridge are equivalent to the interrupt pins on the device side in the table below - INTA#,INTB#, INTC#, and INTD#.

In Reverse mode, INTA#,INTB#, INTC#, INTD# of the PCIe bridge are equivalent to the interrupt pins on the device side in the table below - INTA#,INTB#, INTC#, and INTD#.

To clarify, the Motherboard side in the table below means the side close to the CPU. If the bridge is built on an add-on card, INTA#,INTB#, INTC#, and INTD# are connected to the corresponding INTA#,INTB#, INTC#, and INTD# on gold fingers.

 

Is the FIFO depth adjustable?

No, FIFO depth is a fixed size.

 

Is the primary PCI bus idle/available for use while traffic moves from S1 to S2?

Yes, the primary PCI bus is idle/available for use while traffic moves from S1 to S2.

Is there a replacement for an obsolete part?

Not all obsolete parts will have a direct replacement. However, we recommended that you contact your regional sales office.

Is there a way to prevent devices on S1 to communicate with devices on S2?

Traffic originating on a bus that has a target address decoding to the same bus is not propagated to other buses. If the target address decodes to the other secondary bus, the transaction is placed into either the posted write buffer or the delayed transaction buffer of that target bus (depending on the PCI command used) and will commence at the other bus when the bridge next receives grant from the arbiter. If the target address decodes to neither secondary bus, and is initiated from a secondary bus, the bridge forwards it to the primary PCI bus by placing the transaction into the proper FIFO for that PCI command. If the initiator is already upstream from the bridge and the target is also upstream from the bridge, the bridge does not claim the transaction. There are no "protected" or "non-transparent" address spaces; one of the above four conditions applies.

 

Is there any loading issue with 2 bridges at a 66 MHz primary bus?

Each bridge based add-in card loads the primary PCI bus by one Load, regardless of the number of devices placed on the secondary buses of that bridge IC. PCI specification revision 2.2 allows 2 loads at 66 MHz and 4 loads at 33 MHz.

Is there any way to program the internal arbiter such that it does not follow the round robin system?

The internal arbiter has two possible priority levels for each secondary bus master device and the bridge itself. These are programmable at configuration register offset 40h. By selecting some devices as high priority and some as low priority, you can give preference to a high bandwidth or time-critical device.

Is this part 5V tolerant, and what signaling environment does it support?

Yes, This part is 3.3V core, but signaling can be at 3.3V or 5V. Two signals are involved P_VIO and S_VIO, according to what these two signals are driven to. The specific primary or secondary bus will be driving either 3.3V signaling or 5V signaling. The input is also 5V tolerant.

 

One of the CLKOUT output signals must be connected to FBCLKIN. The length of this trace must equal to other CLKOUT output signal traces?

Yes, all CLKOUT output traces must have the same length.

Should AD, CBE, and PAR signals on PCI Bus be pulled up too?

No, AD, CBE, and PAR signals do not require pull-up resistors. Their states are ensured by PCI bus parking.

To which version of the Intel 21154 is the PI7C8154 pin compatible?

This bridge is designed to Intel 21154BE capabilities (power management support at pin D11, 2KV ESD rating, 0.35 micron process, and more robust tolerances for 3.3V/5V power start up sequence.) The bridge also can be used in designs intended for 21154 versions AC, AE, and BC also.

Voltage on "MSK_IN" pin must kept stable. How do we achieve this?

MSK_IN pin is multi-functional. One of its functions is the input for shift registers to enable and disable the corresponding CLKOUT signal (Please refer to register description: SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h). This is a legacy PCI function. Please see the legacy application circuit below. However, most designers do not use this legacy circuit anymore. Instead, EEPROM or firmware is used to configure the registers. In the case, MSK_IN must be pulled down through 1k-ohm resistor or grounded to keep voltage stable. Keeping the voltage level stable will ensure no interference occurs to the shift registers.

What are the differences of INTA_L, INTB_L, INTC_L, and INTD_L in forward mode and reverse mode?

In Forward mode, INTA_L, INTB_L, INTC_L, and INTD_L are input signals. Interrupt signals of downstream PCI devices should be connected to them.

In Reverse mode, INTA_L, INTB_L, INTC_L, and INTD_L are output signals, and should be connected to interrupt signals of CPU.

 

What are the differences of PERST_L and RESET_L in forward mode and reverse mode?

Forward mode:

PERST_L is an input signal. CPU drives the reset signal to the PCIe bridge.

RESET_L is an output signal to control the downstream PCI devices connected to the PCIe bridge.

Reverse mode:

RESET_L is an input signal. CPU drives the reset signal to the PCIe bridge.

PERST_L is an output signal to control the downstream PCIe device connected to the PCIe bridge.

 

What are the types of jitter?

There are several types of jitter, but the main ones are: cycle-to-cycle jitter, period jitter, half period jitter, and peak-to-peak jitter. Jitter terminology can be found in AB36: Jitter Measurement Techniques at Application Brief No. 36 or Application Note No. 27.

What are Transparent and Non-transparent modes?

In Transparent mode, the PCIe bridge appears transparent to CPU and PCI end devices. In this mode, CPU communicates to the PCI end devices as if they are directly connected.

Non-transparent mode is usually for multi-CPU scenarios, where individual CPU needs to be segmented in order to associate specific CPU to PCI end devices. In this mode, CPU can not directly communicate the PCI end devices, and the PCIe bridge must translate the addresses for them.

 

What do I need to do to modify my driver to take advantage of Pericom's cache line size 0 application performance improvement?

Detect the address of the PCI bridge (since the address will change according to slot on the motherboard and according to the motherboard). Make a PCI type 1 Config Read at the above bus/device/function=0/offset=0C with size of 1 Dword.Use the AND operation: (with the above Dword AND FFFFFF00h).So that bits [0 to 7] are cleared to 0. Use PCI type 1 configuration write to write the new value to bus/device/function=0/offset=0C.That is the entire modification needed.

 

What is a PCI-to-PCI Bridge?

PCI-to-PCI-Bridge is a chip that has a PCI interface on the one side (we call it the primary bus), and it also has another PCI Interface (this is called the secondary bus) on the other side. It is a chip that allows you to add another PCI bus onto your system.

What is a Reversible Bridge?

The PCIe bridge can be configured via “REVRSB” strap pin to work in Forward or Reverse mode.

In Forward mode, the device is capable of PCIe-to-PCI bridging and fan-out, I.e., CPU ←PCIe→ the PCIe bridge ←PCI→ PCI end devices. The device is connected to CPU via PCIe interface and to up to 8 PCI devices via PCI interface. In this mode, CPU handles the PCIe bridge as a PCIe end point, and for the PCI end devices, the PCIe bridge acts as a PCI host.

 In Reverse mode, the device is capable of PCI-to-PCIe bridging, I.e., CPU ←PCI→ the PCIe bridge ←PCIe→ PCIe end device. the PCIe bridge in Reverse mode is useful in the application where the CPU has only PCI interface, but needs to connect to PCIe end device. In this mode, CPU handles the PCIe bridge as a PCI device, and for the PCIe end device, the PCIe bridge acts as the root complex.

 

What is the bandwidth of PCI ports of PI7C9X110?

PI7C9X110's PCI ports are a 32-bit PCI interface and capable of 66MHz clock rate.

What is the bandwidth of PCI ports of PI7C9X111?

PI7C9X111SL's PCI ports are a 32-bit PCI interface and capable of 66MHz clock rate.

What is the bandwidth of PCI ports of PI7C9X130?

PI7C9X130's PCI ports are a 64-bit PCI-X interface and capable of 133MHz clock rate.

What is the bandwidth of PCIe port of PI7C9X130?

PI7C9X130's PCIe port is a x4 PCIe interface and capable of 2.5Gb/s clock rate.

What is the data width and maximum frequency of the 8152?

This is a 32-bit, 66 MHz PCI-to-PCI bridge that adheres to the PCI specification rev 2.2, PCI-to-PCI bridge spec 1.1.

 

 

What is the data width and maximum frequency of the PI7C8150?

This is a 32-bit, 66 MHz PCI-to-PCI bridge that adheres to the PCI specification rev 2.2, PCI-to-PCI bridge spec 1.1.

 

What is the junction temperature of the 8150?

Junction temperature, at peak traffic/peak operating frequency:Tj = Ta +P [Theta Ja]. For the ND (256 pin BGA) part, Theta Ja is 31.2 °C/watt; the MA part uses Theta Ja of 39 °C/watt. Peak traffic/66 MHz on both PCI buses uses 1.39 W power. If we use those numbers in the formula: Tj = 85 °C +1.4w[31.2 °C] ? 125.6 C (256 pin BGA, package ND)Tj = 70 °C + 1.4w[39 °C] ? 124.6 C (208 pin FQFP, package MA) We know the component performs according to all rated specifications until junction temp exceeds at least 125 C.Typical power consumption at 33 MHz primary bus /33 MHz secondary bus is somewhat less than half, around 600mW. See packaging mechanicals for more information.

 

What is the lead finish for Pericom products? What about lead-free?

All Pericom's products that are not lead-free are composed of 85% Sn and 15% Pb. For lead-free products, they are composed of 100% matte Sn. Lead-free products are marked and ordered with the letter "E" suffix at the end of the part number.

What is the length of trace that high speed PCIe signals support, and how is the length calculated if backplane is used?

Many factors affect length of the trace that can be supported including PCB material, connector, etc. Please refer to PCIe Specification. If the trace length is longer than expected, or if backplane is used, we recommend that PCIe re-drivers be used to improve the signals.

 Please contact Pericom FAE for Re-Driver product information.

 

What is the requirement of power-up sequence for PI7C9X110?

PI7C9X110 requires 3.3V power supply before 1.8V.

What is the requirement of power-up sequence for PI7C9X111?

PI7C9X111SL requires 3.3V power supply before 1.0V.

What is the requirement of power-up sequence for PI7C9X130?

PI7C9X130 requires 3.3V power supply before 1.8V.

What is the Vendor and Device ID # for thePI7C8150?

"VendorID = 12D8 h

DeviceID = 8150 h"

 

What is the Vendor and Device ID # for thePI7C8152?

"VendorID = 12D8 h

DeviceID = 8152 h"

 

What is the Vendor and Device ID # for thePI7C8154?

"Vendor ID = 12D8 h

Device ID = 8154 h"

 

What power up sequence is needed for the PI7C7300?

We expect core Vcc (3.3V) to be present before IO is present for hot-swap applications. Hot-swap applications will need a hot-swap controller and external switches to limit induced current through the bridge. For power on ramping, we expect 3.3V and 5V to begin ramping at the same time, so that the delta between them stays around 1.7V or less, on the assumption some devices will have pull-ups to Vio, which might be tied to 5V.

 

What should be done to CFN_L pin in Reverse Mode?

In Reverse Mode, CFN_L pin should be pulled up through a 1k-ohm resistor.

What should be done to CLKIN, CLKOUT, and FBCLKIN pins in Reverse Mode?

In Reverse Mode, FBCLKIN is the PCI clock input, which should get PCI clock source from CPU or system, i.e. 33MHz. CLKIN pin is not used, and should be pulled down through a 1k-ohm resistor. CLKOUT is not used, and should be left floating.

What should be done to CLKRUN_L pin if Clock Management function is disabled?

It is recommended that CLKRUN_L pin is pulled down through a 1k-ohm resistor. Please refer to PCI Mobile Design Guide and PCI Express Card Electromechanical Specification for more details on Clock Management.

What should be done to PME_L pin in Reverse Mode?

In Reverse Mode, PME_L is an output pin, and should be connected to PME_L pin on CPU side through a 5.1k-ohm pull-up resistor.

What should be done to REQ and GNT pins in Reverse Mode?

In Reverse Mode, REQ0 is an input pin, and should be connected to GNT pin on CPU side. GNT0 is an output pin, and should be connected to REQ on CPU side.

What should I do with the PCI interface if I intend to use it in 32-bit mode?

Per PCI Specification, 64-bit ports are compatible with 32-bit mode. AD[63:32], C/BE[7:4], PAR64, REQ64#, and ACK64# signals should be pulled up through a 5.1k-ohm resistor.

 DEV64 signal should be pulled down to indicate 32-bit mode.

 

What should I do with unused REQ# and GNT# signals?

Pull up the unused REQ# signals; you may use a single resistor in the 5K-8K ohm range tied to Vio to reduce parts count. GNT# is an output from our bridge IC and can be left not connected.

 

What's the difference between Intel and Pericom FIFO sizes?

(From http://www.intel.com/design/bridge/index.htm ) The Intel 21154 has (in bytes) . Primary write = 88 bytes , read = 72 bytes, Delayed entries =3 secondary write= 152 bytes . read =152 bytes,Delayed entries= 3 . For the Pericom PI7C8154: (posted write buffer and delayed transaction buffer data size for FIFOs)primary write= 128+128 bytes. Read= 128+128 bytes. Delayed entries= 8. The same for the secondary.Thus the Pericom 8154 has MORE FIFO buffering than Intel.

 

When PCI bus is working in 32-bit mode, what should be done to the ACK64# and REQ64# pin on the PCI slot?

These two signals should be pulled up through a 5.1k-ohm resistor.

Please refer to PCI Specification 4.4.1 for more information.

 

When using the PI7C7300 in hot-swap hardware, which Vcc do I connect it to?

According to the hot-swap specification revision 1.0., the bridge should be connected to early power. All other chips on the board should be connected to switched power, which comes later, driven from the Hot-swap controller.

 

Where are the MS0 & MS1 pins in Pericom PI7C8150 PBGA pci-pci bridge device?

MS1 (pin 106 for package MA-208) is pin R16 for the BGA 8150. It is normally connected to VSS. MS0 (pin 155 for package MA-208) is pin B14 for the BGA 8150. It is normally connected to VDD.

 

Where can I find Mean Time Before Failure (MTBF) or Failures In Time (FIT) values for Pericom products?

FIT and MTBF data can be found at Pericom's Quality webpage.

Where can I find the information on your Pb-free and "Green" packaging?

Lead (Pb)-Free and Green information can be found on individual datasheets or Pb-Free & Green Page.

Which 100MHz differential clock generators do you recommend?

We recommend Pericom's own PI6C557-03PI6C20400, and PI6C20800 models, which are specifically designed to provide PCIe differential clock sources. PI6C557-03 provides 2-channel output, while PI6C20400 provides 4-channel and PI6C20800 provides 8-channel. PI6C557-10 is capable of PCIe differential clock output and 33MHz clock output simultaneously.

 Please contact Pericom FAEs for more information.

 

Which EEPORM models are compatible with PI7C9X110?

PI7C9X110 is compatible with AT24C02B, AT24C04B, AT24C08B, AT24C16B, and other compatible EEPROM models. However, AT24C64 is not recommended due to the addressing method of this model.

Which EEPORM models are compatible with PI7C9X111?

PI7C9X111SL is compatible with AT24C02B, AT24C04B, AT24C08B, AT24C16B, and other compatible EEPROM models. However, AT24C64 is not recommended due to the addressing method of this model.

Which EEPORM models are compatible with PI7C9X130?

PI7C9X130 is compatible with AT24C02B, AT24C04B, AT24C08B, AT24C16B, and other compatible EEPROM models. However, AT24C64 is not recommended due to the addressing method of this model.

Which PCI Bus signals should be pulled up?

Per PCI Specification 4.3.3, the following PCI Bus signals should be pulled up through a 5.1k-ohm resistor: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, INTA#, INTB#, INTC#, INTD#, REQ64#, and ACK64#.

 Pull-up resistors are required on main board, but not on add-on card.

In forward mode, the PCIe bridge requires pull-up resistors on PCI side. In reverse mode, the PCIe bridge requires pull-up resistors on CPU side.

 

Why are MS0 and MS1 signals also listed as VDD and VSS pins?

These are actually multiplexed pins. By default, we are compatible with the Intel 21150 solution, where pin 155 is VDD, and pin 106 is VSS. In future versions of this chip, changing the setting (pulled HIGH or LOW) on these pins will allow for future features. For now, these optional capabilities are reserved.

 

Why do I need a PCI-to-PCI-Bridge?

There are many uses for this chip including:

1) To alleviate the excessive loading on the motherboard. This chip can be used on a server board, or a main board in a system that needs many I/O cards connected to it; these I/O cards can be Ethernet, Fiberchannel, SCSI, or any other PCI I/O cards. PCI specification rev 2.2 allows you to have as many as 4 slots @ 33 MHz slots and two 66 MHz slots. If your system requires more then 4 slots, then you need to add a PCI-to-PCI Bridge. This bridge will take one load only, but it will allow you to add four additional slots on the other side. See Figure 1 of application note 55 available on the web.

2) If you have more than one PCI interface chip on an add-in card. If you are designing an intelligent add-in card that requires a CPU and an I/O chip like Ethernet, SCSI, or Fiberchannel, then you will have two or more PCI loads, in this case you must have a PCI-to-PCI bridge on the card. The PCI specification rev 2.2 allows only one PCI Load connected to the PCI Edge connector. See Figure 3 of Application Note 55 available on the web.

3) If you have many types of interfaces, and you would like to isolate each application’s traffic to a specific bus (example: you have couple of Ethernet chips on your system that need to be 32-bit and 66 MHz and have two low-performance 32-bit applications like modem cards running at 33 MHz). In this case, to isolate the two distinct applications you would add one bridge for the 66 MHz high-speed I/O interfaces, and another bridge for the low-speed applications. The benefit is that the high speed I/O card does not have to wait for the low-speed application to finish its transfer. You will also have one bus running at 66 MHz and another slow bus running at 33 MHz.

Why is the software unable to detect the PCIe bridge in Non-Transparent Mode?

In Non-Transparent Mode, the “class code” of the PCIe bridge is not one of a regular device. And therefore, the BIOS does not list the PCIe bridge in the device list.

In this mode, in addition to the electrical handling in board design to isolate two sides of the PCIe bridge, software driver is needed and bridge needs to be configured correctly for the system to work correctly.