HiFlex Clock

FAQ

At what frequency does the PLL shut down?

Pericom PLL automatically shuts down when the input clock is from several MHz to 20MHz. The actual values depend on the specific product. Lower frequencies will results in higher jitter. Please check with the datasheet or contact technical support:  http://www.pericom.com/support/contact-pericom-support/

Can HCSL clock drive CML clock input?

Yes, just use 0.01uF AC coupling drive CML input. It is normal to see the HCSL swing shrink due to the CML input internal 50 ohm termination.

Can LVPECL drive HCSCL clock input?

Yes, most HCSL inputs accept LVPECL or LVDS DC coupling drive with a 100 ohm cross on differential pair in front of HCSL input, the same as LVPECL/LVDS differential RX termination.

Can the PI6C24xx family support spread spectrum? If so, what is the SSC spread and modulation frequency?

The PI6C24xx family are capable of supporting spread spectrum. The PI6C24xx family has a SSC spread of + / - 0.5% with modulation frequency of 33KHz.

Can the PI6C25xx family support spread spectrum? If so, what is the SSC spread and modulation frequency for Pericom's PI6C25xx family?

The PI6C25xx family are capable of supporting spread spectrum. The PI6C25xx family has a SSC spread of + / - 0.5% with modulation frequency of 33KHz.

Can the PLL be used in bypass mode in a real application even if the datasheet said it is only for test purposes?

Although the datasheet mentioned that it is only for test purposes, there should be no problem to use the bypass mode in a real application. In bypass mode, the PLL will be off and the clock device will function as a normal clock buffer with delay.

Does clock IC Xin pin accept CMSO input?

Yes, the Xin pin can be looked as a CMOS input so can be driven in DC or AC coupling. For lower CMOS voltage swing driver than the clock IC VDD, it has to use AC coupling drive.

How can a single-ended signal interface to a differential driver?

To interface a single-ended signal to a differential driver, connect the single-ended signal to one of the differential input of the driver. The second differential input should be connected to VDD/2. If no VDD/2 source is present, use a voltage divider circuit. See Application Note 56.

How can we determine the external loading capacitors (C1 and C2) for IC’s Xin and Xout pins?

It is suggested: C1=C2=2 *CL – Cstray

Typically Cstray = 4 ~ 6pF

CL is crystal datasheet spec. value, meaning the crystal will oscillate at “0” ppm if the crystal is parallel with the CL For crystal frequency =>20MHz, C1=C2=2*(CL-6) is a good use formula, but always check datasheet recommendation. The C1 and C2 value can be fine tuned for more accurate ppm on board bring up.

 

How come the SuperClock Q4x rising edge alignment is different from other vendors?

Pericom offers two options in the SuperClock family. One has a suffix with a letter “A” and one without. The part number with letter “A” suffix has 4Qx falling edge aligned with the 3Qx rising edge, similar to other vendors. The part number without the letter “A” suffix has 4Qx rising edge align with 3Qx rising edge.

How do I choose a clock IC product?

Pericom's portfolio of  Clock IC include:

• None PLL clock buffers
• Clock generators with synthesized combined output frequencies
• HiFlex clock generators for Telecom, Datacom, Ethernet, etc.

Customers can go to company website and use the Product Finder to locate  the ideal product to match your applications needs or contact sale and marketing person.

 

 

 

How do I choose crystal to match clock IC?

Choose crystal size for your PCB planning first. Then choose crystal datasheet CL = 16 or 18pF for example, which means to get “0” ppm oscillation if total external load cap. equivalently equals to CL.
Lastly,  determine the external load cap. C1 and C2. Always check datasheet for the recommended external load capacitor value since some IC design may have portion on-chip cap already.

How do I determine if the device supports industrial temperature or commercial temperature ranges.

Devices that support industrial temperature will be specified in the datasheet to support a temperature range of -40C to +85C. For commercial temperature range, the datasheet will specify that the device supports temperature ranges of 0C to +70C.

How do I know if a device has been obsoleted? I am unable of find the datasheet on the Pericom website.

If the datasheet is not found on Pericom's website, it is a strong indication that the part has been obsoleted. there are several ways to find out.  The first method would be to check on the Product Detail page for your particular product choice, if there are related PDN notices, they will show up on the tab, marked "PDNS".

Alternatively go Discontinuation Notices to search for the part number.

How long does it take for the PLL to lock?

Pericom's PLL clocks will lock within a few milliseconds or less.

How should unused input and output pins be terminated?

Input pins should never be left open or floating. The system may false trigger from noise if the inputs are left floating. It is recommended that all unused input pins be tied to a valid logic level using a resistor. The advantage of using pull-up or pull-down resistors is that they ensure a defined logic levels when the bus is floating. Typical resistor values range from 1 k-ohm to 10 k-ohms. Outputs may be left floating.

I am unable of find the datasheet on the Pericom website.

If the datasheet is not found on Pericom's website, it is a strong indication that the part has been obsoleted. Try the search tool on the  Pericom website: http://www.pericom.com/support/quality/discontinuation-notices/ or contact your regional sales office.

If the device has an LVPECL interface, can it interface with PECL?

Yes, LVPECL and PECL can interface with each other. However, sometimes a resistor network is required to adjust the common mode voltage. See Application Note No. 7.

Is it a concern to have Vcc reach a certain voltage level before applying a signal to the REF input of the SuperClock?

Unlike other competitors, Pericom's SuperClocks have no issues with power sequencing.

Is it necessary to use a separate dedicated power plane for AVcc?

It is recommended, but not required to have a dedicated AVcc power plane. It is also recommended to use wide trace for power and ground signals.

Is it possible to use the PI6CV855 for DDR400?

For DDR400 it is recommended to use the PI6CV857 rather than thePI6CV855. The PI6CV857 has been tested and verified for DDR400 application which require VCC at 2.6V rather than 2.5V.

Is there a replacement for an obsolete part?

Not all obsolete parts will have a direct replacement. However, we recommended that you contact your regional sales office.

Is there any data on the output skew for same package but different bank? The data sheet didn't seem to specify this parameter. This would be the skew between outputs on different banks when both banks are driven with the same clock.

The output-to-output skew is typically 250ps or less on the same device unless otherwise specified on the datasheet.

To have good termination, I need the value of Rout. Where can the Rout data be found?

R(out) data can be found in the IBIS model located under "pull up" and "pull down". Data should be taken at ~1V and using the equation Rout=V/I.

What are the causes of jitter?

Jitter can be cause by: poor decoupling to the Vcc and GND, signal source with heavy jitter, slow edge rate which will provide additional time to introduce jitter to the signal. Additional information can be found in Application Note 24: Designing for Minimal Jitter when using Clock Buffers

What are the types of jitter?

There are several types of jitter, but the main ones are: cycle-to-cycle jitter, period jitter, half period jitter, and peak-to-peak jitter. Jitter terminology can be found in AB36: Jitter Measurement Techniques at Application Brief No. 36 or Application Note No. 27.

What do I need to do with the feedback loop if the bypass mode is used?

In bypass mode, the PLL is shut off; therefore there is no need to connect the FB loop. It can be left floating or used as an extra output.

What is cycle-to-cycle jitter?

Cycle-to-cycle jitter is the difference in the clock's period between two consecutive cycles and is expressed in units of + pico-seconds. This is because it can be either leading or lagging from the ideal output waveform.

What is half-period jitter?

Half-Period Jitter is the measure of maximum change in a clock's output transition from its ideal position during one-half period. It is measured as: tjit(half-period) = thalf-period n – 1/2 ƒo, where ƒo is the frequency of the input signal.

What is HiFlex clock IC?

PI6LCxxxx is Pericom's newly developed high frequency, very low jitter clock generator family, which use high Q silicon VCO to dramatically reduce traditional PLL clock jitter. They are especially good for Telecom, Datacom, and Ethernet for phase jitter <=1 ps designs.  HiFlex Clock FInder tool

What is LVDS clock and its termination?

LVDS is IEEE standard Low Voltage Differential Logic signal, typically =1.2+/-200mV. Its termination only needs an equivalent 100 ohm across pair at receive side either on PCB or internal ASIC.
Check ASIC datasheet for no double termination.

What is LVPECL clock and its termination?

LVPECL is Low Voltage Positive (supply) Emitter Couple Logic. Its voltage level is around 2V+/-400mV and the most use termination is 150 ohm pull-down at output pin and AC or DC coupling to an equivalent 100 ohm across pair at RX ASIC side. Check ASIC datasheet  to prevent double termination.

What is recommend for unused output pins?

Unused output can be left floating. However, it is recommended that the input pins are either tied to VCC or GND with a 1 k-ohm to 10 k-ohm resistor to prevent any unknown states.

What is the correct capacitor value in the feedback loop in PLL clocks?

The correct capacitor depends on the actual feedback trace. Typical design uses feedback capacitor in the range of 0pF to 12pF.

What is the difference between the PI49FCT3807BH and the PI49FCT3807HB?

The PI49FCTxx suffix is reversed on package top mark, but it is the same part. For the PI49FCTxx, there are usually three additional letters. They are the speed grade, package type, and the part number codes. A detailed explanation can be found Here.

What is the ICC current for a device operating at a certain frequency?

ICC value will change with frequency and loading. As frequency increases, the ICC value will also increase. This trend also applies to loading. As loading increase, ICC value will increase.

What is the lead finish for Pericom products? What about lead-free?

All Pericom's products that are not lead-free are composed of 85% Sn and 15% Pb. For lead-free products, they are composed of 100% matte Sn. Lead-free products are marked and ordered with the letter "E" suffix at the end of the part number.

What is the maximum input frequency for the A version of the PI49FCTxxx?

A, B, C, D and Blank indicate the speed grade specified on the datasheet. Typical operating frequency for these speed grades are as followed: A:33MHz, B:66MHz, C:80MHz and D: 133MHz.

What is the output impedance and how does it relate to drive strength?

Output impedance is the resistance between the NMOS and Ground when the device is driving low and the resistance between the PMOS and Vcc when the device is driving high. The driver strength is inversely proportional with output impedance. A lower output impedance will result in higher driver strength.

What is the output when the input signal to the PLL is removed?

Some of Pericom's PLL's have the output oscillate for a short period of time (around 5ms) when the input signal is removed. But it will eventually settle down to a DC low or a DC high.

What is the required input clock jitter for a PLL based clock buffer?

The most ideal is to have as minimal input jitter as possible since the input jitter will contribute additional jitter to the output.

What is the termination resistor value needed for a specific clock device?

The value of the termination resistor depends on the output impedance of the device. It must meet the equation: Zo + Zseries = Ztrace

What type of decoupling is needed for clock devices?

We recommend following JEDEC recommendation by using the following filter circuit for AVcc: place the 2200pF capacitor close to the PLL, use a wide trace for the PLL analog power and ground, connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL), and recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8-ohm DC max, 600-ohm @ 100MHz).

Where can I find information on wave soldering temperature, IR Reflow or Vapour Reflow Temperature?

For reflow and soldering temperature information, please visit Pericom's Quality webpage.

Where can I find Mean Time Before Failure (MTBF) or Failures In Time (FIT) values for Pericom products?

FIT and MTBF data can be found at Pericom's Quality webpage.

Where can I find the information on your Pb-free and "Green" packaging?

Lead (Pb)-Free and Green information can be found on individual datasheets or Pb-Free & Green Page.

Where can I find the Thermal Resistance values (Theta JA, JC) and Mean Time between Failure Rate for doing Thermal & Reliability calculations?

Theta JA and JC can be found at the following link: Packaging Page. Other quality information can be found at Quality Page.

Where can I find the Thermal Resistances for Junction to Board, Junction to Case and Junction to Ambient (0 fps air)?

Pericom does not have any thermal data relating to the board or case. Other quality information can be found at Quality Page.

Where is the proper oscilloscope probe position for high frequency clock?

It is suggested that always put test probe at the closest RX receive end point, RX input pin, or BGA via, to prevent reflection test influence, with very short GND wire. Otherwise, the waveform will be distorted. Application Note AN021

 

 

 

Why do you need to be careful for layout of crystal PCB circuit?

The IC Xin pin is the most sensitive pin as crystal amplifier input. Make Xin and Xout pins to crystal trace routing in narrow loop with load caps. close on the same layer with crystal. The 2nd layer GND plane must be continuously underneath them with reasonable keep-out (>200mil) of any board vias around the crystal area to get rid of board noises.

Why is the top marking on the FCT devices different from the datasheet?

Sometimes the speed grades and the package nomenclature for our FCT devices may be swapped around. Full explanation for nomenclature information can be found here, under “Packaging Support Documentation”.